Exemplary embodiments relate to communications, and more specifically, to creating randomly ordered fields while maintaining the temporal ordering.
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors (or any other hardware that may, e.g., be the device under test) to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. In this paradigm, a processor executes instructions in an order governed by the availability of input data, rather than by their original order in a program. In doing so, the processor can avoid being idle while data is retrieved for the next instruction in a program, processing instead the next instructions which is able to run immediately.
For in-order processors, the processing of instructions is normally done in these steps: 1) Instruction fetch. 2) If input operands are available (in registers for instance), the instruction is dispatched to the appropriate functional unit. If one or more operand is unavailable during the current clock cycle (generally because they are being fetched from memory), the processor stalls until they are available. 3) The instruction is executed by the appropriate functional unit. 4) The functional unit writes the results back to the register file.
For out-of-order processors, this paradigm breaks up the processing of instructions into these steps: 1) Instruction fetch. 2) Instruction dispatch to an instruction queue (also called instruction buffer or reservation stations). 3) The instruction waits in the queue until its input operands are available. The instruction is then allowed to leave the queue before earlier, older instructions. 4) The instruction is issued to the appropriate functional unit and executed by that unit. 5) The results are queued. 6) Only after all older instructions have their results written back to the register file, then this result is written back to the register file.